1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method of fabricating a nonvolatile memory device. Although the present application is suitable for a wide scope of applications, it is particularly suitable for minimizing an effective size of a nonvolatile memory device.
2. Discussion of the Related Art
Generally, a memory cell determines packing density of a nonvolatile memory devices such as electrically erasable programmable read only memory (EEPROM) and flash EEPROM. Effective size of such a memory cell is determined by size and array of the cell. For example, the memory cell has a minimum cell structure using a simple stacked-gate structure.
Recently, as demand in the nonvolatile memory such as flash EEPROM and a flash memory card has been increased, the nonvolatile memory has been actively researched throughout the industry.
Nonetheless, when the nonvolatile semiconductor memory devices is applied for mass storage media, there is an obstacle yet to be overcome. For example, cost per bit in the nonvolatile semiconductor memory is still too expensive. Furthermore, a low power consuming memory chip is required for application to portable electronics. As a result, to reduce the cost per bit in the nonvolatile memory device, a multi-bit cell has been studied recently.
Since the conventional nonvolatile memory stores only one bit data in one memory cell, its packing density has a one-to-one relationship with the number of the memory cell. On the other hand, a multi-bit cell has a high packing density without reducing the size of the memory cell since two or more bit data are stored in one memory cell.
To realize such a multi-bit per cell, three or more threshold voltage levels should be programmed in the respective memory cell. For example, to store two bit data per cell in a memory cell, four threshold voltage levels (2.sup.2 =4) should be programmed. At this time, four threshold voltage levels are logic values 00, 01, 10, and 11, respectively.
However, even in the multi-level programming, there is a problem that a respective threshold voltage level has a distribution value of about 0.5V.
Since such a distribution value is reduced by exactly adjusting the respective threshold voltage levels, it is possible to program more threshold voltage levels, thereby increasing the number of bits per cell. To reduce such a voltage level, a method of repeatedly performing programming and monitoring has been adopted.
In such a method, to program the nonvolatile memory cell at a desired threshold voltage level, a series of program voltage pulses are applied to the cell. To monitor whether the cell has reached a desired threshold voltage level, the threshold voltage of the programmed memory cell is read. In the course of monitoring, programming is completed if the monitored threshold voltage level reaches a desired threshold voltage level value.
However, in repeatedly performing programming and monitoring, it is difficult to reduce an error distribution of threshold voltage level due to a limited program voltage pulse width. Moreover, since the algorithm for repeatedly performing programming and monitoring is realized by means of circuits, problems arise where an area of a peripheral circuit for the memory chip increases and programming time takes longer.
FIGS. 1A and 1B are a cross-sectional view and a circuit diagram illustrating a conventional simple stacked nonvolatile memory device, respectively.
As shown in FIG. 1, a floating gate 3 is formed over a p-type semiconductor substrate 1. A tunneling oxide film 2 is formed between the floating gate 3 and the p-type semiconductor substrate 1. A control gate 5 is formed over the floating gate 3. A dielectric film 4 is formed between the control gate 5 and the floating gate 3. An n-type source region 6a and an n-type drain region 6b are formed in the p-type semiconductor substrate 1 at both sides of the floating gate 3.
In the conventional simple-stacked nonvolatile memory cell, a coupling coefficient becomes smaller as the effective cell size of the nonvolatile memory cell is reduced. To solve such a problem, the dielectric film 4 may be formed using oxide-nitride-oxide (ONO) structure. However, this structure causes complicated process steps and also requires a high temperature annealing process.
Meanwhile, as shown in FIG. 1B, the nonvolatile memory cell includes a floating gate 3, a control gate 5 for controlling the charge amount provided to the floating gate 3 for programming, and a field effect transistor for reading (or monitoring) the charge amount provided to the floating gate 3 during programming. The field effect transistor includes a floating gate 3, a source 6a, a drain 6b, and a channel region 7 between the source 6a and the drain 6b.
The aforementioned nonvolatile memory cell is operated when a current flows between the drain 6b and the source 6a if a sufficient voltage for programming is applied to the control gate 5 and the drain 6b.
Then, the current is compared with a reference current. If it is the same as or less than the reference current, a programming completion signal is generated and the programming is completed.
The conventional nonvolatile memory device will be described with reference to the accompanying drawings.
FIG. 2A is a circuit illustrating a conventional nonvolatile memory device. FIG. 2B is a circuit illustrating another conventional nonvolatile memory device having a simple stacked structure without metal contact. FIG. 2C is a circuit illustrating another conventional nonvolatile memory device having no metal contact, in which a source and a drain are separated from each other.
As shown in FIG. 2A, a plurality of metal bit lines 9 are disposed in a column direction at a predetermined interval. A plurality of word lines 10 are disposed in a direction perpendicular to the metal bit lines 9. A common source line 11 per two word lines 10 is disposed in the same direction as the word lines 10.
The drains 6b of a pair of cells in the nonvolatile memory device are connected to the metal bit lines 9 and the sources 6a are connected to the common source line 11. Since a metal contact 8 per two cells is required, the effective size of the memory cell becomes significantly large. Therefore, although the conventional nonvolatile memory cell array has a minimum cell size of a simple stacked structure, the effective cell size is substantially limited by the pitch of the metal contact 8.
To solve such a problem, a nonvolatile memory cell array without metal contact 8 has been proposed to reduce the number of the overall metal contacts. In other words, the nonvolatile memory cell array having a simple stacked cell structure without metal contact can provide with a minimum effective cell size.
However, in the nonvolatile memory cell array having no metal contact, a programming disturbance occurs during programming or erasing a non-selected cell adjacent to the word line direction.
Thus, instead of the nonvolatile memory cell array having no metal contact, a nonvolatile memory cell array having an asymmetrical split-channel cell structure including a selection gate 12 has been used to solve such a problem, as shown in FIG. 2B. In this case, the programming disturbance can be avoided during programming due to hot electron injection and also over-erasing can be eliminated.
As shown in FIG. 2B, the nonvolatile memory device includes a plurality of word lines 10 disposed on a semiconductor substrate (not shown) at a predetermined interval, a plurality of bit lines 13 perpendicular to the word lines 10 to form a plurality of squares at a predetermined interval, and a plurality of memory cells disposed one by one in respective squares.
The respective nonvolatile memory cell of FIG. 2B includes a floating gate 3, a control gate 5 for controlling the amount of charge provided to the floating gate 3 for programming, and a field effect transistor for reading or monitoring the charge amount provided to the floating gate 3 during programming.
Specifically, the field effect transistor includes a floating gate 3, a source 6a, a drain 6b, and a channel region 7 between the source 6a and the drain 6b.
The control gate 5 of the respective nonvolatile memory cell is coupled to the adjacent word line 10. The source 6a of the nonvolatile memory cell in one square is coupled to the adjacent bit line 13 in common with the drain 6b of the nonvolatile memory cell in the next square.
Also, a selection transistor 12 is coupled to the bit line 13. A metal contact 8 per thirty-two nonvolatile memory cells or more is connected to the selection transistor 12 in a column direction. Thus, effective cell size can be reduced. However, in this case, there is a problem that the size in unit cell increases due to a gate of the selection transistor. Particularly, it is difficult to perform programming by tunneling of low power operation. The reason why is that two cells adjacent to the word line direction are subject to the same bias condition as each other, as easily recognized by the drawing.
To solve such a problem and to enable tunneling programming, the nonvolatile memory device having no metal contact, in which a source and a drain are separated from each other, has been proposed, as shown in FIG. 2C.
In such a nonvolatile memory device, a plurality of metal data lines 9 are disposed in a column direction at a predetermined interval. A plurality of bit lines separated by a source line 15 and a drain line 14 are disposed in the same direction as the metal data lines 9.
The source 6a of the nonvolatile memory cell of FIG. 1B is coupled to the source bit line 15 and its drain 6b is coupled to the drain bit line 14.
A metal contact 8 is connected to the respective metal data line 9. The control gate 5 is connected to the respective word lines 10 in a direction perpendicular to the bit line separated by the source bit line 15 and the drain bit line 14. However, in the aforementioned structure, there is a problem in that the size in unit cell increases due to a separation of the bit lines.
FIG. 3 is a cross-sectional view illustrating a conventional nonvolatile memory device having a split-channel cell structure with a split-gate.
As shown in FIG. 3, a floating gate 3 is formed over a P type semiconductor substrate 1. A tunneling oxide film 2 is formed between the floating gate 3 and the P type semiconductor substrate 1. A control gate 5 is formed over the floating gate 3. An insulating film 16 is formed over the P type semiconductor substrate 1 including the control gate 5 and the floating gate 3. A selection gate 17 is formed on the insulating film 16. A dielectric film 4 is formed between the control gate 5 and the floating gate 3. A source 6a is formed in the P type semiconductor substrate 1 at one side of the floating gate 3 to be offset with respect to the floating gate 3. A drain 6b is formed in the P type semiconductor substrate 1 at the other side of the floating gate 3.
FIG. 4A is a cross-sectional view illustrating a conventional nonvolatile memory device having a split-channel cell structure. FIG. 4B is a cross-sectional view illustrating a conventional nonvolatile memory device of FIG. 4A in a channel width direction.
In the conventional nonvolatile memory device having a split-channel cell structure, as shown in FIG. 4A, a floating gate 3 is formed over a P type semiconductor substrate 1 at a predetermined interval. A control gate 5 is formed over the floating gate 3. Subsequently, a tunneling oxide film 2 is formed between the floating gate 3 and the P type semiconductor substrate 1. A dielectric film 4 is formed between the floating gate 3 and the control gate 5.
A source 6a is formed in the P type semiconductor substrate 1 at one side of the floating gate 3 to be offset with the floating gate 3. A drain 6b is formed in the P type semiconductor substrate 1 at the other side of the floating gate 3.
In the nonvolatile memory device shown in a channel width direction, as shown in FIG. 4B, a field oxide film 18 for insulation between cells is formed on the P type semiconductor substrate 1 at a predetermined interval. A gate insulating film 19 is formed on the P type semiconductor substrate 1 between the respective field oxide films 18.
A floating gate 3 is formed on the gate insulating film 19 to overlap the adjacent field oxide film 18. A dielectric film 4 is formed on a predetermined region of the floating gate 3. A control gate 5 is formed on the dielectric film 4.
A gate cap insulating film 20 is formed on the control gate 5. An insulating film sidewall spacer 21 is formed at both sides of the gate cap insulating film 20 and the control gate 5. An erasing gate 17 is formed on the field oxide film 18 and the gate cap insulating film 20. A tunneling oxide film 22 is formed respectively at both sides of the floating gate 3 and the adjacent erasing gate 17.
However, the aforementioned conventional nonvolatile memory device has a problem in that although the memory cell array of a simple stacked cell structure having no metal contact may provide a minimum effective cell size, it also causes undesired program disturbances.